AREA & POWER OPTIMIZATION OF AES ALGORITHM USING MODIFIED MIXCOLUMN WITH COMPOSITE S-BOX

Abstract

AES algorithm has attracted from various departments since it gives a very high level of security and can be implemented easily. Cryptographic applications are based on application- specific- integrated circuit (ASIC) technology, and it is to provide sufficient security level. AES Encryption and Decryption of Cryptographic algorithm plays an vital role in mail delivery system and banking due to increasing demand for secure transformation and transactions respectively. In this article, the proposed enhanced Inverse Mix-Column with Composite S-Box is designed for AES encryption and decryption. In existing AES Mix-Column, more number of logic gates are used to perform the multiplication of input stage bytes. In order to reduce this problem, the proposed enhanced Inverse Mix-column with composite S-Box is designed. This method which is used to reducing the logic gates. In addition, the proposed Inverse MixColumn is integrated into AES decryption for improving the performance of the architecture. The enhanced Inverse Mix-Column transformation with composite S-Box is to reduce the latency, area and power consumption and also reducing the hardware complexity of AES.