DESIGN OF RELIABLE NETWORK ON CHIP (NOC) ROUTER BASED PACKET SWITCHING METHOD

Abstract

Network- on- Chip (NOC) has developed as a new model to integrate large number of cores on a single silicon die. The NOC architecture is the on-chip
communication infrastructure consist of physical layer, the data link layer and the network layer of OSI protocol stack. In this paper, NOC router based packet switching network with Round Robin Arbiter is proposed. In packet switching method, data’s are transmitted in short packets. Packets are received, stored briefly and forward to the next node. The packet switching network with virtual channel flow control provides the flexibility, area and  energy efficiency and also . All packets are routed through the shortest paths and maintaining the performance of Noc in the presence of faults. The main goal of this work is to reduce the frequent checking of unconnected nodes and making the return path delay. In this proposed design, is to reduce the power, delay and area and also improves the performance of the architecture. NoC data transport medium is occupied by routers, which is predominantly occupied by FIFO buffers and routing logic. Arbiter is used in network on chip when number of input are requested for same output port , the arbiter has produce the signal on the basis of that number of input port getting a priority and the input port transmit a packet to output port.