SIMULATION ENHANCEMENT OF IMPROVING FPGA DEBUG METHODOLOGIES BY USING HAMMING SEC- DAED-TAED CODE

Abstract

In the debug system, logic analyzer is built into FPGA. The debug module allows non-interfering real time debugging of software for the SoC microcontroller. Post –processing and analyzing the data is invaluable for system debugging. The prototype using trace- buffers to note a subset of internal signals into an on-chip memory for subsequent analysis. In this paper, high frequency methods are not suited for monitoring the fault occurrence in trace buffers. Therefore,
low frequency method which is used to detect and correct the faults in trace buffers. The internal stages of the circuits are monitored and identified the faults and these faults are stored in the separate memory for analyzing the signals. In the proposed, the two methodologies are used.1) Finite State Machine (FSM) and 2) Hamming codes. The clock pulses are then divided by using  clock divider. The finite state machine is used to monitor the errors and also the hamming codes are used to detect and correct the errors. Thus the tracing buffers are performed to monitor the signal state on FPGA.