An Optimized Fused Add-Multiply (FAM) Operator

Abstract

Now a day’s Digital Signal Processing (DSP) are widely used by many manufacturers in Integrated Circuit (IC) and Embedded Industries. The commonly used functional units in the DSP Processors are controller unit, memory unit, Arithmetic logical unit (ALU). ALU unit will consist of MAC unit, MAD unit. Large number of arithmetic operations are carried out by DSP processors of which mostly used operator is Add-Multiply (AM). Here we mainly focus on fusion of add unit and Modified Booth (MB) unit, thereafter called as Fused Add Multiply (FAM) unit which is used for recoding in multiply operation. A Wallace Carry Save Adder (CSA) tree is used to reduce delay for addition of partial products. The overall result is generated by a Carry Propagate Adder (CPA). Comparing with the existing system, the proposed system yields considerable performance in critical delay, power consumption, and area.