VLSI Based Minimized Composite S-Box and Inverse Mix Column for AES Encryption and Decryption

Abstract

Advanced Encryption Standard (AES) is one of the best cryptography algorithms in secured data communication. Due to provide efficient security, AES consumes more hardware complexity and power consumption. In addition, speed of the AES is low due to complexity in data flow path. Substitution Box (S- Box), Shift Rows, MixColumn multiplication and Add Round Key are the four fundamental steps in AES algorithm. Among those four steps, S-Box and Inverse MixColumn multiplication (decryption of MixColumn) are recognized as a high potential steps, because both S-Box and MixColumn multiplication consumes more hardware complexity and power consumption. In this paper, Enhanced Inverse MixColumn multiplications are used to reduce the hardware complexity of AES algorithm. In addition to enhanced Inverse MixColumn multiplications, architecture of composite S-Box is realized to minimize the hardware complexity of AES. Further minimized composite S-Box and enhanced Inverse MixColumn multiplication transformations are integrated into AES algorithm to increase the efficiency of AES in terms of less area utilization, high speed and low power consumption. Implementation of minimized AES composite S-Box and enhance inverse MixColumn transformations are done in the field of Very Large Scale Integration (VLSI).