Design and Implementation of a Novel Bi-Recoder Based Digital FIR Filter

Abstract

In this paper, an efficient direct form Finite Impulse Response (FIR) filter is designed to enhance the speed and throughput of digital filtering mechanism. Multiplication and Accumulation (MAC) units are to be recognized as high potential for the design of FIR filter. To enhance the performances of MAC unit for digital FIR filter, a novel Bi-Recoder based multiplier is developed in this paper through Very Large Scale Integration (VLSI) System design environment. Less silicon area utilization, lower power consumption and high speed are the main concerns of VLSI System design. Reduced complexity Square Root Carry Select Adder (SQRT CSLA) is one of the best digital addition mechanisms to perform the accumulation of two large N-bit binary values. In this research work, reduced complexity SQRT CSLA is to be considered to support the addition process of Bi- Recoder multiplier. Finally, the design of a novel reduced complexity SQRT CSLA based Bi- Recoder multiplier is incorporated into digital FIR filter to enhance the performances of filtering mechanisms in terms of VLSI concerns. Proposed model of digital FIR filter utilizes the less hardware and high speed than other best existing model of digital FIR filters.