DESIGN OF LOW POWER 8T-XOR BASED 1 BIT-FULL ADDER USING CMOS

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Published Oct 30, 2018
DOI https://doi.org/10.5281/ijrset.v3i10.174

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SabariManoj N
M.E VLSI DESIGN,Easwari Engineering College,Ramapuram,Chennai
Suriya K
M.E, Assistant Professor,Easwari Engineering College,Ramapuram,Chennai.

Abstract

This paper puts forward a methodology for designing 1 bit full adder using a 8T XOR. The 8T XOR is combined in a specific manner to get a full adder with sum and
carry output. The resulting 1 bit full adder is made up of 22 transistors. The simulation is done using Tanner EDA (Electronic design automation) tool using 250nm technology and 5V power supply. The results show the efficiency of the parameters. 

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Issue
Vol 3 No 10 (2016): Volume 3 Issue 10
Section
Articles