DESIGN OF LOW POWER 4-BIT FULL ADDER CIRCUIT USING CMOS LOGIC

Abstract

This paper presents a performance analysis of hybrid 1-bit full-adder circuit design. The adder cell is dissected into smaller modules. The modules are analyzed and calculated extensively. To achieve a good-drivability, noise-robustness, and low-energy operations for deep sub micrometer to explore hybrid-CMOS style design. Hybrid-CMOS design style uses various CMOS logic style circuits to construct new full adders with desired performance .In this paper, a hybrid 1-bit full adder design employing both complementary metal oxide semiconductor (CMOS) logic and transmission gate logic is reported. In the proposed design of this paper first implemented for 1-bit full adder and then extended for 4 bit full adder circuit. The circuit was implemented by using Tanner EDA (Electronic design
automation) tool. The 4 bit full adder circuit, which is used to improve the performance of the ALU operation. The proposed 4 bit full adder design is to enhance the speed of the operation and also reduces the area, latency and power consumption. The proposed 4-bit full adder circuit has energy efficient and outperforms several standard full adders without trading off driving capacity and reliability. The new 4-bit full-adder circuit successfully operates at low voltages. Performance parameters such as power consumption, delay and layout area were compared with the existing 1-bit full adder designs such as complementary pass-transistor 
logic, transmission gate adder and function-adder, hybrid pass-logic with static CMOS output drive full adder, and so on.